Two-sided die in a four-sided leadframe based package

ABSTRACT

A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.

CLAIM OF PRIORITY

This application is a continuation of U.S. patent application Ser. No.11/770,066 filed on Jun. 28, 2007 to be issued as U.S. Pat. No.8,395,246, entitled “TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASEDPACKAGE”, which application is incorporated herein by reference in itsentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate to a method of fabricating asemiconductor package, and a semiconductor package formed thereby.

2. Description of the Related Art

As the size of electronic devices continue to decrease, the associatedsemiconductor packages that operate them are being designed with smallerform factors, lower power requirements and higher functionality.Currently, sub-micron features in semiconductor fabrication are placinghigher demands on package technology including higher lead counts,reduced lead pitch, minimum footprint area and significant overallvolume reduction.

One branch of semiconductor packaging involves the use of a leadframe,which is a thin layer of metal on which one or more semiconductor dieare mounted. The leadframe includes electrical leads for communicatingelectrical signals from the one or more semiconductors to a printedcircuit board or other external electrical devices. Commonleadframe-based packages include plastic small outlined packages (PSOP),thin small outlined packages (TSOP), shrink small outline packages(SSOP) and thin quad flat packages (TQFP). These packages include leadswhich extend out from the sides of the encapsulated package, which leadsmay be surface mounted to a host device such as a printed circuit board(PCB) as by soldering. Another common type of leadframe-based package isa leadless package. These include dual flat no-lead (DFN) and quad flatno-lead (QFN) packages. These packages do not have leads extending outof the sides of the package, but instead have exposed terminals at abottom surface of the package for soldering to a host device such as aPCB. The leadframe package shown in FIGS. 1 and 2 may be used in eitherleaded (e.g., TSOP) or leadless (e.g., DFN) packages.

FIG. 1 shows a leadframe 20 before attachment of a semiconductor die 22.A typical leadframe 20 may include a number of leads 24 having firstends 24 a for attaching to semiconductor die 22, and a second end (notshown) for affixing to a printed circuit board or other electricalcomponent. Leadframe 20 may further include a die attach pad 26 forstructurally supporting semiconductor die 22 on leadframe 20. While dieattach pad 26 may provide a path to ground, it conventionally does notcarry signals to or from the semiconductor die 22. In certain leadframeconfigurations, it is known to omit die attach pad 26 and instead attachthe semiconductor die directly to the leadframe leads in a so-calledchip on lead (COL) configuration.

Semiconductor leads 24 may be mounted to die attach pad 26 as shown inFIG. 2 using a die attach compound. Semiconductor die 22 isconventionally formed with a plurality of die bond pads 28 on at leastfirst and second opposed edges on the top side of the semiconductor die.Once the semiconductor die is mounted to the leadframe, a wire bondprocess is performed whereby bond pads 28 are electrically coupled torespective electrical leads 24 using a delicate wire 30. The assignmentof a bond pad 28 to a particular electrical lead 24 is defined byindustry standard specification. FIG. 2 shows less than all of the bondpads 28 being wired to leads 24 for clarity, but each bond pad may bewired to its respective electrical lead in conventional designs. It isalso known to have less than all of the bond pads wired to an electricallead as shown in FIG. 2.

FIG. 3 shows a cross-sectional side view of leadframe 20 andsemiconductor die 22 after the wire bond process. Once wire bonding iscompleted, a molding process is performed to encase the components in amolding compound 34 to form the finished package. It is known to recessor “down-set” the semiconductor die within the leadframe, as shown inFIG. 3, in order to balance the semiconductor die against the forces ofthe molding compound as it flows around the die and leadframe.

As shown in FIGS. 2 and 3, it is typical to have bond pads 28 on firstand second opposite sides of the semiconductor die 22 for electricalcoupling with their respective leads. According to industryspecification and ease of design, bond pads 28 along the first edge ofthe semiconductor die connect to respective leadframe leads adjacent tothe first edge of the semiconductor die, and bond pads along the second,opposite edge of the semiconductor die connect to respective leadframeleads adjacent to the second edge of the semiconductor die.

In an effort to reduce semiconductor die form factor, it is now known toprovide bond pads on certain semiconductor die, such as for example ASICcontrollers, along only one edge of the die, or two adjacent edges asshown in FIG. 4. A problem with such configurations is that four-sidedleadframes generally do not have enough leads on a single side toaccommodate all of the die bond pads along the edge of a die having padsalong one or two edges (there would be more die bond pads along a sidethan is shown in FIG. 4).

It is currently known to provide a BGA (Ball Grid Array) package toconnect to two-sided die. BGA packages provide the advantage that theyhave high pin-out density and are able to connect to each of the diebond pads in a flip-chip arrangement. However, BGA packages areexpensive and not desirable for certain applications. It is thereforedesirable to provide a four-sided leadframe capable of connecting to allof the die bond pads along one or two edges of a semiconductor die.

SUMMARY OF THE INVENTION

The present invention, roughly described, relates to a method offabricating a leadframe-based semiconductor package, and a semiconductorpackage formed thereby. In embodiments, a semiconductor die having diebond pads along two adjacent edges may be electrically coupled to foursides of a four-sided leadframe. A first embodiment relates to alead-based leadframe such as TQFP. In such an embodiment, a pair ofsides of the leadframe adjacent the bond pad edges of the die include aplurality of conventional electrical leads which terminate a shortdistance from the first side for connection to the adjacent bond pads.The remaining pair of sides of the leadframe distal from the bond padedges of the die each may include one or more elongated electricalleads. These elongated electrical leads extend from their respectivesides into an interior of the leadframe and terminate adjacent the diebond pads.

In one embodiment, the elongated leads may be provided over a topsurface of the semiconductor die, i.e., on a same side of the die as thedie bond pads. In this embodiment, during fabrication, the leadframe maybe flipped over, and the die may be lowered onto the leadframe with thedie bond pads facing the leadframe. Once affixed, the leadframe and diemay be flipped over and the bond pads may be wire bonded to the leadsand elongated leads on the four sides of the leadframe. In analternative embodiment, the elongated leads may be provided beneath thesemiconductor die.

A further embodiment relates to connecting a semiconductor die with bondpads along two adjacent edges to a four-sided QFN leadframe. In thisembodiment, a group of terminals on two adjacent sides are electricallycoupled to a die attach paddle in a center of the leadframe. Thereafter,a semiconductor die may be bonded to the leadframe off-center. Namely,the edges of the die not having die bond pads may be positioned over thegroup of terminals coupled to the die attach paddle. Thereafter,terminals from all four sides of the leadframe may be wire bonded to thesemiconductor die. All of the terminals from the two sides of theleadframe spaced from the die may be wire bonded to the die bond pads.Also, terminals from the remaining two sides which are not electricallycoupled to the die attach paddle may be wire bonded to the die bondpads. The terminals coupled to the die attach paddle are not used forsignal transfer to or from the semiconductor die.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an exploded perspective view of a conventional leadframe and asemiconductor die.

FIG. 2 is a perspective view of a semiconductor die affixed to aconventional leadframe.

FIG. 3 is a cross-sectional view of a conventional leadframe-basedsemiconductor package.

FIG. 4 is a perspective view of a conventional semiconductor die havingdie bond pads along two adjacent edges.

FIG. 5 is a top view of a leadframe according to an embodiment of thepresent invention including a semiconductor die affixed to electricalleads of the leadframe.

FIG. 6 is a top view of a leadframe according to an alternativeembodiment of the present invention including a semiconductor dieaffixed to electrical leads of the leadframe.

FIG. 7 is a cross-sectional side view of the leadframe and semiconductordie of FIG. 5 or 6 encapsulated in mold compound to form a semiconductorpackage.

FIG. 8 is a top view of a QFN leadframe according to an alternativeembodiment of the present invention.

FIG. 9 is a top view of the QFN leadframe of FIG. 8 having asemiconductor die attached thereto.

FIG. 10 is a top view of a leadframe according to a further alternativeembodiment of the present invention.

FIG. 11 is a top view of the leadframe of FIG. 10 including asemiconductor die attached thereto.

DETAILED DESCRIPTION

Embodiments of the present invention will now be described in referenceto FIGS. 5-11 which in general relate to a method of fabricating asemiconductor package, and a semiconductor package formed thereby. It isunderstood that the present invention may be embodied in many differentforms and should not be construed as being limited to the embodimentsset forth herein. Rather, these embodiments are provided so that thisdisclosure will be thorough and complete and will fully convey theinvention to those skilled in the art. Indeed, the invention is intendedto cover alternatives, modifications and equivalents of theseembodiments, which are included within the scope and spirit of theinvention as defined by the appended claims. Furthermore, in thefollowing detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be clear tothose of ordinary skill in the art that the present invention may bepracticed without such specific details.

FIG. 5 is a top view of a leadframe 100 including a semiconductor die102. In general, the leadframe 100 according to the present inventionmay be batch processed from a panel of such leadframes to achieveeconomies of scale. Leadframe 100 further includes electrical leads 112for communicating electrical signals to and from the semiconductor die102 and an external electronic device, such as a printed circuit board,on which the finished package is mounted. As explained hereinafter,leads 112 include a group of elongated leads 112 a for coupling to diebond pads 114 positioned along an adjacent side of the leadframe. Theleadframe 100 may be a TQFP (four-sided) leadframe, but it is understoodthat other types of leadframe packages may be used, such as PSOP, TSOPand SSOP leadframes.

As explained hereinafter, the die 102 may mount directly on leads 112 ain an LOC (lead-on-chip) or COL (chip-on-lead) arrangement. Although notcritical to the present invention, the semiconductor die 102 may forexample be a flash memory chip (NOR/NAND), SRAM or DDR, or a controllerchip such as an ASIC. It is understood that the leadframe 100 and die102 may be used in a variety of different types of semiconductorpackages. The die 102 may further include die bond pads 114 for couplingto the electrical leads 112 as explained hereinafter. It is understoodthat leadframe 100 may include greater or fewer leads 112 than are shownin the figures, and it is understood that semiconductor die 102 wouldlikely include more die bond pads 114 that are shown, but may includeless in embodiments of the invention. It is also understood that not alldie bond pads 114 need be coupled to a lead 112 in embodiments of theinvention.

Leadframe 100 may be formed of a planar or substantially planar piece ofmetal, such as copper or copper alloys, plated copper or plated copperalloys, Alloy 42 (42Fe/58Ni), or copper plated steel. Leadframe 100 maybe formed of other metals and materials known for use in leadframes. Inembodiments, leadframe 100 may also be plated with silver, gold, nickelpalladium, or copper.

Leadframe 100 may be formed by known fabrication processes, such as forexample, chemical etching. In chemical etching, a photoresist film maybe applied to the leadframe. A pattern photomask containing the outlineof the leads 112 and other features of leadframe 100 may then be placedover the photoresist film. The photoresist film may then be exposed anddeveloped to remove the photoresist from areas on the conductive layersthat are to be etched. The exposed areas are next etched away using anetchant such as ferric chloride or the like to define the pattern in theleadframe 100. The photoresist may then be removed. Other known chemicaletching processes are known. The leadframe 100 may alternatively beformed in a mechanical stamping process using progressive dies. As isknown, mechanical stamping uses sets of dies to mechanically removemetal from a metal strip in successive steps.

Leadframe 100 includes four sides 104, 106, 108 and 110. Each sideincludes a plurality of leads 112, each having a first end for couplingto a bond pad of die 102 via a wire bond, and a second end opposite thefirst end for connection to an external host device such as a printedcircuit board (not shown). Leadframe 100 may be fabricated with leads112 including a group of elongated leads 112 a. Leads 112 a may extendinto a center of the leadframe, an area typically reserved for thesemiconductor die in conventional leadframes. In general, leads 112 aare provided to extend to a position adjacent the die bond pads 114along an adjacent edge of leadframe 100. Thus, in the embodiment shownin FIG. 5, the leads 112 a on side 110 extend into the middle of theleadframe 100, and then toward side 104 where they terminate adjacent todie bond pads 114. Similarly, the leads 112 a on side 108 extend intothe middle of the leadframe 100, and then toward side 106 where theyterminate adjacent to die bond pads 114.

While FIG. 5 shows a group of four elongated leads 112 a projecting fromeach of sides 108 and 110, it is understood that a group of one to threeleads 112 a, or more than four leads 112 a, may project from a givenside to connect with one or more die bond pads along the adjacent edgeof leadframe 100. Moreover, while FIG. 5 shows a group of leads 112 aextending into the center and then out to the adjacent leadframe side,those of skill in the art would appreciate a wide variety of otherconfigurations of leads 112 and 112 a that may be formed on leadframe100 during the fabrication of leadframe 100. In embodiments, the leads112 of leadframe 100 allow the semiconductor die 102 to be used in anindustry standard pin-out configuration.

One example of an alternative configuration is shown in FIG. 6. In FIG.6, a group of leads 112 a from side 110 which are located adjacent toside 104 extend straight into the center of leadframe 100 where theyterminate without extending toward side 104. Leads 112 a extending fromside 110 in FIG. 6 are close enough to bond pads 114 adjacent to side104 for wire bonding as is known and as is explained hereinafter. Inembodiments such as shown in FIG. 5, the leads 112 a emanating from side108 may be the same shape as, but the mirror image of, the leads 112 aemanating from side 110. As shown in FIG. 6, the adjacent sides whichinclude elongated leads 112 a need not have the same configurations ofelongated leads 112 a.

After formation of the leadframe 100, the die 102 may be mounted toleads 112 a of leadframe 100. In embodiments, leadframe 100 may beflipped over so that the surface opposite that seen in FIGS. 5 and 6faces upward. Similarly, die 102 may be flipped over and lowered ontoleadframe 100 so as to be supported on portions of leads 112 a. Die 102may then be attached to leads 112 a using a dielectric die attachcompound, film or tape. It is also contemplated that a dielectric spacerlayer may be provided between die 102 and leads 112 a in embodiments.After the die 102 is securely affixed to the leadframe 100, theleadframe and die may again be flipped over to be in the orientationseen in the top views of FIGS. 5 and 6, and the cross-sectional view ofFIG. 7.

Thereafter, wire bonds 116 may be formed in a known manner electricallycoupling die bond pads 114 to leads 112 and leads 112 a. In particular,with reference for example to FIG. 6, die bond pads 114 adjacent to side106 may be coupled by wire bond to leads 112 along side 106.Additionally, leads 112 a protruding from side 108 may also be affixedto die bond pads 114 adjacent side 106, from a side of die bond pads 114opposite leads 112 from side 106.

After leads 112 (including leads 112 a) are wire bonded to die bond pads114, leadframe 100 and die 102 may be encapsulated in a mold compound118 in a known encapsulation process to form a completed portable memorypackage 120 as shown in FIG. 7. Mold compound 118 may be an epoxy suchas for example available from Sumitomo Corp. and Nitto Denko Corp., bothhaving headquarters in Japan. Other mold compounds from othermanufacturers are contemplated. The mold compound 118 may be appliedaccording to various processes, including by transfer mold or injectionmold techniques to form package 120. The ends of leads 112 protrude frommold compound 118 and may be surface mounted to a host device such as aPCB to electrically and physically couple the package 120 to the hostdevice.

FIGS. 8 and 9 are top views of a leadframe 200 according to analternative embodiment of the present invention. Analogous componentsfrom FIGS. 5 through 7 are indicated in FIGS. 8 and 9 with theirreference number incremented by 100. Leadframe 200 may be a QFN-typeleadframe including a plurality of terminals 212 and 224 around foursides 204, 206, 208 and 210. Leadframe 200 further includes a die attachpaddle 222 in a center of the leadframe which may be used as a heat sinkand ground plane for a semiconductor die affixed to leadframe 200.

In accordance with the embodiment shown in FIGS. 8 and 9, a group ofterminals 224 may be electrically coupled to the die attach paddle 222.The terminals 224 may be defined during the formation of leadframe 200to be grounded to die attach paddle 222. Alternatively, they may beformed as terminals 212 and then grounded to die attach paddle 222 as bysoldering or other electrical coupling. As explained below, theseterminals do not function to transfer signals to or from a semiconductordie mounted on leadframe 200. It is known to half-etch portions of a QFNleadframe, to secure the half-etched portions within a mold compound.Details relating to a half-etched leadframe are disclosed for example inU.S. Pat. No. 6,674,156, entitled, “Multiple Row Fine Pitch LeadlessLeadframe Package With Use of Half-Etch Process,” which patent isincorporated by reference herein in its entirety. The grounded terminals224 may be half-etched to ensure a secure positioning of the terminalswithin the mold compound discussed below.

As shown in FIG. 9, a semiconductor die, such as for examplesemiconductor die 102 described above, may be affixed to leadframe 200using a known die attach compound, film or tape. According to thisembodiment, die 102 may be attached off-center in a corner of leadframe200 on die attach paddle 222 and on terminals 224 grounded to the dieattach paddle 222. In particular, the two edges of die 102 not havingbond pads 114 are positioned over grounded terminals 224. Thus, in theexample of FIG. 9, die 102 is positioned in the lower right hand cornerof leadframe 200. Such positioning of die 102 allows wire bonds to beformed between die bond pads 114 and sides 204 and 206, and portions ofsides 208 and 210 as explained below.

After mounting of the semiconductor die 102 as shown in FIG. 9,terminals 212 along the sides of leadframe 200 spaced from die 102 maybe wire bonded to die bond pads 114 using wire bonds 216 in a known wirebond process. Moreover, in embodiments, terminals 212 (i.e., thoseterminals not grounded to the die paddle 222) on the sides of leadframe200 adjacent to die 102 may also be bonded to die bond pads 114 via wirebonds 216. For example, in FIG. 9, terminals 212 on side 208 locatednext to grounded terminals 224 may be affixed to bond pads 114 onsemiconductor die 102 and terminals 212 on side 210 located next togrounded terminals 224 may be affixed to bond pads on semiconductor die102. Terminals 224 are not wire bonded to die 102 and are not used forsignal transfer to or from die 102. While all of the terminals beneaththe die 102 are shown as grounded terminals 224, it is understood thatone or more of the terminals beneath the die need not be grounded.

As die 102 is mounted in a corner of leadframe 200, access to the diebond pads 114 for wire bonding is allowed from all four sides of QFNleadframe 200. That is, as shown in FIG. 9, all of the terminals 212along sides 204 and 206 may be wire bonded to die 102 and portions ofthe terminals 212 along sides 208 and 210 may be wire bonded to die bondpads 114.

The leadframe 200 and coupled die 102 may next be encapsulated in a moldcompound, such as described above with respect to FIG. 7, resulting in astandard form factor QFN package. Terminals 212 of the QFN package maybe surface mounted to a host device such as a PCB to electrically andphysically couple the QFN package to the host device.

A further embodiment of the present invention is shown in FIGS. 10 and11. This embodiment may be similar to the embodiment of FIGS. 5 through7, but in the embodiment of FIGS. 10 and 11, the elongated leads areprovided underneath the semiconductor die. Analogous components fromFIGS. 5 through 7 are indicated in FIGS. 10 and 11 with their referencenumber incremented by 200. Leadframe 300 may be a lead-type leadframeincluding a plurality of leads 312 around four sides 304, 306, 308 and310. Leadframe 300 may further include a die attach paddle 322 forsupporting a semiconductor die, such as semiconductor die 102 describedabove. Paddle 322 may be omitted in alternative embodiments.

As shown in FIG. 11, a semiconductor die 102 having bond pads 114 may beattached to paddle 322 and/or leads 312 a using a dielectric die attachcompound, film or tape. Leads 312 a may extend into a center ofleadframe 300 and out to a position adjacent the die bond pads 114 alongan adjacent edge of leadframe 300. Thus, in the embodiment shown in FIG.10, the leads 312 a on side 310 extend into the middle of the leadframe300, and then toward side 304 where they terminate adjacent to die bondpads 114. Similarly, the leads 312 a on side 308 extend into the middleof the leadframe 300, and then toward side 306 where they terminateadjacent to die bond pads 114.

While FIG. 10 shows a group of four elongated leads 312 a projectingfrom each of sides 308 and 310, it is understood that a group of one tothree leads 312 a, or more than four leads 312 a, may project from agiven side to connect with one or more die bond pads 114 along theadjacent edge of leadframe 300. Moreover, while FIG. 10 shows a group ofleads 312 a extending into the center and then out to the adjacentleadframe side, those of skill in the art would appreciate a widevariety of other configurations of leads 312 and 312 a that may beformed on leadframe 300 during the fabrication of leadframe 300.

Once the die is affixed to the leadframe 300, wire bonds 316 may beformed in a known manner electrically coupling die bond pads 114 toleads 312 and leads 312 a. After leads 312, 312 a are wire bonded to diebond pads 114, leadframe 300 and die 102 may be encapsulated in a moldcompound in a known encapsulation process to form a completed portablememory package. The ends of leads 312 may protrude from the package andmay be surface mounted to a host device such as a PCB to electricallyand physically couple the package to the host device.

In embodiments, a spacer layer (not shown) may be affixed to generallyhorizontal surfaces of electrical leads 312 a on a side of electricalleads 312 a opposite semiconductor die 102. In embodiments, the spacerlayer may be a dielectric material such as for example a polyimide filmor tape, or epoxy resins (FR-4, FR-5) or bismaleimide triazine (BT),affixed to electrical leads 312 by a known adhesive compound. Thethickness of the spacer layer may vary in alternative embodiments. Itmay happen during encapsulation that leads 312 a are forced downward andpossibly exposed to the exterior on a surface of the mold compound. Thespacer layer may be used to ensure that the leads remain buried withinthe package. The spacer layer may also provide structural stability toleads 312 a. A similar spacer layer may be used in the embodiment shownin FIGS. 5 through 7 in embodiments.

Embodiments of the present invention described thus far have included asingle semiconductor die 102. It is understood that more than onesemiconductor die may be included in at least some of the packagesdescribed above. Moreover, while embodiments of the invention describedabove are directed to connecting four sides of a leadframe to asemiconductor die having bond pads along two adjacent edges, it iscontemplated that embodiments of the present invention may connect two,three or four sides of a leadframe to a semiconductor die having bondpads along a single edge.

The foregoing detailed description of the invention has been presentedfor purposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise form disclosed. Manymodifications and variations are possible in light of the aboveteaching. The described embodiments were chosen in order to best explainthe principles of the invention and its practical application to therebyenable others skilled in the art to best utilize the invention invarious embodiments and with various modifications as are suited to theparticular use contemplated. It is intended that the scope of theinvention be defined by the claims appended hereto.

We claim:
 1. A leadframe for receiving a semiconductor die having diebond pads along a first edge of the semiconductor die, the leadframecomprising: a first set of electrical terminals on a first side of theleadframe positioned adjacent to the die bond pads along the first edgeof the semiconductor die; and a second set of electrical terminals on asecond side of the leadframe adjacent and perpendicular to the firstside of the leadframe, the second set of electrical terminals includingends extending to and positioned adjacent to the die bond pads along thefirst edge of the semiconductor die.
 2. The leadframe of claim 1,wherein the second set of electrical terminals extend in from the secondside of the leadframe and then out toward the first side of theleadframe.
 3. The leadframe of claim 1, wherein the leadframe is aQFN-type leadframe.
 4. A leadframe for receiving a semiconductor diehaving die bond pads along a first edge, the leadframe comprising: afirst side of the leadframe lying adjacent the first edge of thesemiconductor die; a first set of electrical leads on the first side ofthe leadframe, the first set of electrical leads including first endspositioned to terminate proximate to the die bond pads along the firstedge of the semiconductor die; and a second side of the leadframeadjacent the first side of the leadframe; a second set of electricalleads on the second side of the leadframe, the second set of electricalleads being longer than the first set of electrical leads and the secondset of electrical leads including first ends positioned to terminateproximate to the bond pads on the first edge of the semiconductor die.5. The leadframe of claim 4, wherein the second set of electrical leadsprotrude from the second side of the leadframe into a center portion ofthe leadframe and then out toward the first side of the leadframe. 6.The leadframe of claim 4, the semiconductor die further includingelectrical leads along a second edge of the semiconductor die adjacentthe first edge, the leadframe further comprising: a third side of theleadframe lying adjacent the second edge of the semiconductor die; athird set of electrical leads on the third side of the leadframe, thethird set of electrical leads including first ends positioned toterminate proximate to the die bond pads along the second edge of thesemiconductor die; and a fourth side of the leadframe adjacent the thirdside of the leadframe; a fourth set of electrical leads on the fourthside of the leadframe, the fourth set of electrical leads being longerthan the third set of electrical leads and the fourth set of electricalleads including first ends positioned to terminate proximate to the bondpads on the second edge of the semiconductor die.
 7. The leadframe ofclaim 6, wherein the fourth set of electrical leads emanate from thefourth side of the leadframe into a center portion of the leadframe andthen out toward the third side of the leadframe.
 8. The leadframe ofclaim 6, wherein the second and fourth groups of electrical leads aremirror images of each other.
 9. The leadframe of claim 4, wherein theleadframe is for a TSOP, PSOP or SSOP.
 10. A leadframe for receiving asemiconductor die having die bond pads along a first edge, the leadframecomprising: a first side of the leadframe lying adjacent the first edgeof the semiconductor die; a second side of the leadframe adjacent thefirst side of the leadframe; a third side of the leadframe adjacent thesecond side of the leadframe; a fourth side of the leadframe adjacentthe third and first sides of the leadframe; a first set of electricalleads on the first side of the leadframe, the first set of electricalleads including first ends positioned to terminate proximate to the diebond pads along the first edge of the semiconductor die; and a secondset of electrical leads on the second side of the leadframe, the secondset of electrical leads including first portions extending from thesecond side of the leadframe toward the fourth side the leadframe, andsecond portions extending from the first portions toward the first sideof the leadframe, the second portions of the second set of electricalleads including ends positioned to terminate proximate to the bond padson the first edge of the semiconductor die.
 11. The leadframe of claim10, the semiconductor die further including electrical leads along asecond edge of the semiconductor die adjacent the first edge, theleadframe further comprising: a third set of electrical leads on thethird side of the leadframe, the third set of electrical leads includingfirst ends positioned to terminate proximate to the die bond pads alongthe second edge of the semiconductor die; and a fourth set of electricalleads on the fourth side of the leadframe, the fourth set of electricalleads including first portions extending from the fourth side of theleadframe toward the second side the leadframe, and second portionsextending from the first portions toward the third side of theleadframe, the second portions of the fourth set of electrical leadsincluding ends positioned to terminate proximate to the bond pads on thesecond edge of the semiconductor die.
 12. The leadframe of claim 11,wherein the second and fourth sets of electrical leads are mirror imagesof each other about a diagonal between the first and second sides andthe third and fourth sides of the leadframe.
 13. The leadframe of claim10, wherein the leadframe is for a TSOP, PSOP or SSOP.